Semiconductor devices are used in many electronic and other applications. Semiconductor devices comprise integrated circuits that are formed on semiconductor wafers by depositing many types of thin films of material over the semiconductor wafers, and patterning the thin films of material to form the integrated circuits.
One type of semiconductor device is a memory device, in which data is typically stored as a logical “1” or “0.” Memory devices may be static or dynamic. Dynamic memory devices need to be refreshed to “remember” the data, whereas static memory devices do not need to be refreshed to retain stored data.
One type of static memory device, also referred to in the art as a non-volatile memory (NVM) device, is a floating gate memory device. Floating gate memory devices can be either erasable programmable read-only memory (EPROM) or electrically erasable programmable read-only memory (EEPROM). Both of these floating gate memories rely on trapping charge in the floating gate by suitable application of a bias to the various terminals of the device. The charge may be trapped by a number of mechanisms comprising carrier tunneling and/or injection. The charge may be removed either electrically as in EEPROM devices or by an external source such as an ultra violet light. The presence of this charge in the floating gate determines the state of the memory as “1” or “0”. The floating gate devices are usually arranged in large arrays to form a memory device such as a Flash memory. Based on the layout of the floating gate transistors, Flash memories may comprise a NOR, NAND, or an AND memory cell. As an example, most commercial memory cards such as memory sticks comprise NAND Flash cells.
Floating gate devices are increasingly used in combination with other CMOS devices and components. A typical floating gate device comprises a double poly stack separated by an insulator, wherein the lower poly forms the floating gate and the upper poly forms the control gate. Such floating gate devices fabricated using a CMOS process flow requires additional processing such as additional mask levels. For example, although the process for forming the control gate poly and logic gate poly can be shared or common with the CMOS devices, forming the floating gate poly requires additional process steps (for example, deposit, pattern and etch). The number of lithography or masking steps correlates to the cost of a process flow. In fact, Flash memory devices typically take about 1.5 times to about 2.5 times more lithography steps than standard CMOS devices. Such a process flow may not be cost efficient, in some cases. For example, if non volatile memories comprise only a small portion of the wafer area, the additional process steps may increase the wafer cost considerably. In some cases, for example, it may not be cost effective to add extra process steps, if the fraction of the memory devices is less than 10% of the total number of devices. Similarly, the total number of memory devices in a memory array may dictate the cost effectiveness of introducing additional process steps. For example, if the memory array has less than 100 devices, it may not be effective to add extra process steps.
Thus, what are needed in the art are cost effective ways of forming CMOS compatible floating gate devices especially when the ratio of memory to logic device is low.